The present invention relates to very large scale integrated circuits (in particular to large static random access memories), and to methods for fabrication thereof.
Interconnect technology is increasingly a major limitation in the fabrication of very large scale integrated circuits. In particular, the use of multiple patterned polysilicon or metal layers for interconnects places great pressure on the processing technology related to etching of contact holes and planarization of interlevel dielectrics. However, the additional routing capability which is provided by any additional level of interconnect will often give circuit designers options which translate into more compact layouts, better circuit performance, and/or greater ease of circuit design.
For these reasons much effort has been dedicated to modifying processes to include a buried contact. A buried contact process is a process which uses a single layer to form not only MOS gates, but also, using other patterned portions of the same layer, contact to the source/drain regions of MOS transistors. That is, the same thin film polysilicon or polycide layer must in some locations be separated from the moat by a very thin high-integrity gate oxide, and in other locations must form an ohmic contact to highly doped moat regions. This leads to three main classes of processing problems: first, gate oxide integrity becomes more difficult to preserve. Second, scalability is limited by interdiffusion between the polysilicon material and the bulk silicon. That is, the phosphorus doping used to make the polysilicon conductive will normally outdiffuse into the silicon substrate at the contact location. However, as devices are scaled to small geometries, this phosphorus diffusion can counterdope a major fraction of the channel stop doping, leading to leakage between active areas. Third, first contacts are highly desirable in CMOS processing, but present technology does not provide any manufacturable process to make contact to P+moat regions. Not only is there the problem of how to avoid a diode between N+poly and P+substrate, but similar problems of dopant outdiffusion may lead to shorting from the poly to the PMOS substrate at first contacts to P+.
There have been published suggestions of ways to provide a local interconnect level in the context of a self-aligned titanium silicide process for source/drain silicidation. The self-aligned titanium silicide source/drain silicidation process is disclosed in U.S. patent application Ser. No. 492,069, filed May 6, 1983U.S. Pat. No. 4,545,116, which is hereby incorporated by reference. In this process, metallic titanium is deposited overall, and is then heated in a nitrogen atmosphere so that the titanium reacts with exposed silicon surfaces (such as source/drain regions, or exposed upper surfaces of polysilicon lines) to form titanium silicide. The portions of titanium which did not react to form silicides are then stripped (using, for example, a wet etch). This process provides a self-aligned silicidation process without any patterning steps. This self-aligned silicidation process has come into wide use in integrated circuit fabrication.
The previously proposed local interconnect schemes based on this process use additional patterned silicon to provide conductive silicide regions extending out over the field oxide as desired. That is, in the process developed by Hewlett Packard and published at Page 118 of the 1984 IEDM Proceedings, (which publication is hereby incorporated by reference), after the titanium metal is deposited overall, and before heat is applied to effect silicide reaction, a thin layer of silicon (either polycrystalline or amorphous) is patterned on top of the titanium metal. Where this silicon layer has been applied, a silicide will form during the reaction process, so that silicides can be formed extending over the gate sidewall oxide or over the field oxide. A similar approach previously developed at Texas Instruments used patterned silicon straps which were applied before the titanium metal was applied.
However, both of these approaches have the limitation that deposition of an additional layer is required. Thus, both of these approaches contain excess processing complexities.
Other publications relevant to examination of the present application may be found in the paper by C. Y. Ting at page 110 of the 1984 IEDM proceedings (and see especially page 113) and in the paper by M. Alperin et al., Development of the Self-aligned TiSi.sub.2 Process for VLSI applications at page 141 of the February 1985 issue of the IEEE transactions on Electron Devices.
It has been discovered that when the direct-react titanium silicide silicidation process is performed in a nitrogen atmosphere, a layer of titanium nitride (TiN) is formed in the titanium metal layer over field oxide. Thus, after the silicide reaction occurs, the portions of the deposited titanium metal layer which have not been in contact with a source of silicon (and therefore have not formed silicide) are not merely unreacted titanium metal, as was previously thought, but include a large fraction of titanium nitride. The present invention makes use of this newly discovered titanium nitride layer to provide a new and advantageous local interconnect method and structure.
After the silicidation step, the titanium nitride layer is patterned and selectively removed from titanium silicide and silicon oxide regions where it is not desired. After this, a final anneal is performed at higher temperature (e.g. 800.degree. C.) to reduce the final sheet resistance of the titanium silicide layers to below one ohm per square.
It is well-known in the integrated circuit art that titanium nitride is conductive, and the use of titanium nitride as a conductive diffusion barrier in contacts has been previously published; but no work published prior to the filing date of the parent application is known to discuss the use of titanium nitride to provide local interconnects, as in the present invention.
The present invention uses a structure wherein moat-to-moat interconnections have been formed using a very thin (e.g. 1000 Angstroms) layer of titanium nitride. This invention provides at least the following advantages:
1. The present invention provides a more compact full-CMOS SRAM cell, for given design rules, than could otherwise be fabricated reliably.
2. The present invention provides a more compact full-CMOS SRAM cell, for given design rules, than any prior-art cell using either metal jumpers or buried contacts.
3. The present invention provides a faster full-CMOS SRAM cell, for given design rules, than could otherwise be fabricated reliably.
4. The present invention provides a full-CMOS SRAM cell which can be fabricated reliably and which makes no use of the metal layers except for power and signal bussing; this advantageously frees the designer's hand in including SRAM blocks in custom or semi-custom logic.
In a 1985 IEDM paper, researchers from Hewlett-Packard proposed applying a sputtered silicon layer over the deposited titanium metal, in a direct-react titanium silicidation process, before the reaction step, to provide patterned local interconnects of titanium silicide. These local interconnects were apparently thought at the time to provide advantages comparable to that of the titanium nitride interconnect of the present invention. However, not only does this approach require greater processing complexity, but it also fails to provide a crucial advantages of the present invention: the titanium silicide provides an efficient diffusion path for boron and phosphorous, and therefore problems of interdiffusion and counterdoping remain acute. By contrast, in the present invention the titanium nitride is a very good diffusion barrier, and these problems do not arise. The phosphorous counterdoping problems of the process shown in the HP 1985 paper may be confirmed by a more recent HP paper which describes a 16K static random access memory implemented with their TiSi.sub.2 strap process, but that only uses it to connect P-type and N-type junctions together. That is, the HP researchers did not use local interconnect to connect gates to junctions. In a design experiment to test the advantages of the present invention, researchers at Texas Instruments laid out a static random access memory cell according to the exact HP layout, i.e. where local interconnect is used to interconnect junctions, and where metal straps plus 2nd contacts are used to cross-couple the gates. In this HP process, the inability to interconnect both the gates and junctions with local interconnect results in a cell size, using 1 micron design rules, that is 75% larger than a cell with the same design rule geometries using TiN for local interconnect. This illustrates the advantage that TiN has over TiSi.sub.2 for performing the local interconnect function.
The present invention provides all the circuit advantages of a buried contact structure, without the costs associated therewith. For example, the present invention also provides a more compact SRAM cell than would be achievable without buried contacts. In addition, the improvements in compactness attained through the present invention are even better than those of conventional prior art buried contacts: since the present invention also permits overlapping the moat contacts onto field oxide, the moat regions can be made minimum geometry, and further area economy results. Moreover, in conventional buried contact approaches, the moat region underneath the buried contact is necessarily screened by polysilicon from the source/drain implantation, so that conventional buried contact methods must rely on interdiffusion effects to make sure that the buried contact does not have excessive spreading resistance. This is not a problem with the present invention, and the scalability of the present invention is therefore superior. A further advantage is that the titanium nitride local interconnect level taught by the present invention is thinner than the polysilicon interconnect used in the prior art of buried contacts, and therefore the topographic excursion introduced by the local interconnect level is less with the present invention.
Major constraints on the prior art of SRAMs have been packing density and speed. The packing density problem arises from the fact that, if the cell is laid out conventionally without using buried contacts, as shown in FIG. 5, use of metal jumpers in necessary, which costs a great area premium. On the other hand, if buried contacts are used, the processing difficulties attendant on patterning the gate oxide result. Moreover, first contacts provide a diffusion path from the polysilicon gate level to moat, and therefore first contacts are typically not reliable in a full CMOS process, since this diffusion path permits the n+of the polysilicon gate level to counterdope the p+source/drain regions.
According to the present invention there is also provided: A static random access memory cell array, comprising
a plurality of static random access memory cells, each comprising PA0 first and second cross-coupled inverters, each said inverter comprising PA0 said gate of at least one of said pull-up and pull-down transistors of said first inverter being connected to a drain of at least one of said pull-up and pull-down transistors of said second inverter through a local interconnect layer, PA0 first and second cross-coupled inverters, each said inverter comprising PA0 first and second access transistors selectably connecting outputs of said first inverter to a first bit line and outputs of said transistors of said second inverter to a second bit line; PA0 wherein both of said respective pull-down transistors within each single one of said cells are formed in a common substrate and are separated one from another by field isolation regions, PA0 and wherein both of said respective pull-up transistors within each single one of said cells are formed in a common substrate and are separated one from another by field isolation regions, PA0 and wherein both of said respective access transistors connected to each single one of said cells
first and second cross-coupled inverters, PA1 each said inverter comprising PA1 a pull-up transistor PA1 and a pull-down transistor PA1 a pull-up transistor PA1 and a pull-down transistor, PA1 each said pull-up transistor and pull-down transistor PA1 said local interconnect layer having a minimum thickness less than that of said gate of said pull-up transistor of said first inverter PA1 and making ohmic contact directly to said gate and to said drain. PA1 a pull-up transistor PA1 and a pull-down transistor; and PA1 are formed in a common substrate PA1 and are separated PA1 by field isolation regions.
all of said respective pull-down transistors within each individual one of said cells being separated one from another by a field oxide region. PA2 having a crystalline channel with a source connected to a substantially constant voltage PA2 and having an insulated gate capacitatively coupled to said channel PA2 and having a drain, PA2 one from another PA2 and from both of said pull-up transistors within said single cell PA2 and from both of said pull-down transistors within said single cell
According to the present invention there is also provided: A static random access memory cell comprising:
According to the present invention there is also provided: A static random access memory cell comprising: